Opcode and Operand

Opcode and Operand

This tutorial tells you all about opcode and operand. You will also come to know about different instruction cycles of instructions.

The machine language consists of strings of binary numbers (that is 0's and 1's), which means the code is written in binary language, and this is the only language that is recognized by the computer system. 


Machine code is the fundamental language of any computer system. Machine language is also named as a low-level language.






What is OPCODE?

Opcode is the first part of an instruction that tells the computer what function to perform and is also called Operation codes. Opcodes are the numeric codes that hold the instructions given to the computer system. 

These are the instructions that describe the CPU what operations are to be performed. The computer system has an operation code or opcode for each and every function given to it.


What is OPERAND?

Operand is another second part of instruction, which indicates the computer system where to find the data or instructions or where to store the data or instructions

The number of operands varies amongst different computer systems. Each instruction indicates the Control Unit of the computer system what to perform and how to perform it. 


The operations are Arithmetic, Logical, Branch operation, so on depending upon the problem that is provided to the computer. 



Different instruction cycles

Registers take place in each instruction cycle. Various registers and instruction cycles are discussed below:


1. Memory Address Register (MAR) - Memory address register is associated with the address lines of the system bus. It defines the address in memory for read and write operation.


2. Memory Buffer Register (MBR) - Memory Buffer Register is associated with the data lines of the system bus. It defines the value that is to be stored in the memory or the last value scanned from the memory.



3. Program Counter (PC) - Program Counter carries the address of the next instruction that is to be fetched.


4. Instruction Register (IR) - Instruction Register holds the last instruction fetched.


The Instruction Cycle - Each and every phase of the instruction cycle can be broken down into a sequence of elementary micro-operations. 

The instruction cycle consists of four cycles i.e., The Fetch Cycle, The Indirect Cycle, The Execute Cycle, and The Interrupt Cycle.


Indirect cycle - The Indirect cycle is always followed by the Execute cycle and the Interrupt cycle is always followed by the Fetch cycle. The next cycle totally depends upon the state of the system.


A 2-bit register called Instruction Cycle Code (ICC) is assumed. It labels the state of the processor. At last of each and every cycle, Instruction Cycle Code (I CC) is set accordingly.



  • Fetch Cycle
  • Indirect Cycle
  • Execute Cycle
  • Interrupt Cycle


The Fetch cycle - At the starting of the fetch cycle, the address of the next instruction that is to be executed is stored in the program counter (PC) registers. 

step - 1. The address in PC is moved to the Memory Address Register (MAR).

step - 2. Address in Memory Address Register (MAR) is located on the address bus, there is READ command on the control bus, result arrives on the data bus, and then it is copied into Memory Buffer Register (MBR). 

The program counter (PC) is increased by 1 in such a way that it get ready for the next instruction.

step - 3. Counter of Memory Buffer Register (MBR) is lifted to the Instruction Register (IR). 

The fetch cycle includes 3 steps and 4 micro-operations. It is to be noted that the second and third micro-operations happen simultaneously during the second time unit.


The Indirect Cycle - When an instruction is fetched, the next step is to fetch source operands that are to be fetched by indirect addressing. 

step - 1. The addressing field of instruction is moved to Memory Address Register (MAR) which is used for fetching the address of the operand. 

step - 2. The address field of Instruction Register (IR) is amended from the Memory Buffer Register (MBR).

step - 3. Instruction Register (IR) is now in the state i.e., IR is ready for execution cycle but it considers interrupt cycle first that's why it skips the execution cycle for a bit.



The Execution Cycle - Unlike the three other cycles, the execute cycle is different. The fetch, indirect, and interrupt cycles are very easy but the execution cycle is different. Let us consider an example of ADD instruction

ADD       R, X

Here, the instruction adds the value of location X to register R. The beginning should be with Instruction Register (IR) containing the ADD instruction.

step - 1. The addition of the Instruction Register (IR) is loaded into the Memory Address Register (MAR).

step - 2. The address field of Instruction Register (IR) is updated from the Memory Buffer Register (MBR). 

step - 3. The value of R and Memory Buffer Register (MBR) is being added by Arithmetic Logic Unit (ALU).


The Interrupt Cycle - When the execution cycle completed, there is a test that is build to check whether an enabled interrupt has arisen or not. 

If an enabled interrupt has arisen, the interrupt cycle also arises. Its nature depends upon the machine.

step - 1. Values of Program Counter (PC) is moved to Memory Buffer Register (MBR).

step - 2. Memory Address Register (MAR) is loaded with an address where the value of the Program Counter (PC) is to be saved. PC is loaded with the address of begin of the interrupt routine.

step - 3. Memory Buffer Register (MBR) having the old value of Program Counter (PC) is stored in memory.
Previous
Next Post »

1 comments:

Click here for comments
Thu Feb 06, 11:34:00 AM 2020 ×

Please mention the cycle and size of instruction.


Congrats bro Ram Sankar Mohanty you got PERTAMAX...! hehehehe...
Reply
avatar

Comment Below: ConversionConversion EmoticonEmoticon